SiGe (silicon-germanium alloy) heterojunction bipolar transistors (HBTs) integrated with standard silicon CMOS forming the so-called SiGe BiCMOS circuits have been developed for analog/mixed signal applications in high-speed wireless and wired network communications. In SiGe BiCMOS, the base layer of the HBT is formed from SiGe alloy, different from conventional Si-only bipolar transistors which have a silicon base. Because of the narrow bandgap of SiGe alloy compared with the bandgap of the silicon emitter, the base layer can be highly doped to reduce the parasitic resistance without sacrificing the emitter efficiency. As a result, SiGe HBTs exhibit higher response frequency and higher gain as compared to the Si counterpart.
A major development in the silicon CMOS technology is the use of silicon-on-insulator (SOI) substrates which are now available commercially.
The integration of BiCMOS with SOI circuits opens another regime of high performance circuits also having low power consumption. Various integration schemes have been proposed previously; e.g. in U.S. Pat. No. 5,587,599 "Bipolar transistor and manufacturing method", which disclosed a CMOS compatible bipolar transistor on an SOI substrate.
Some other prior publications such as S. Parke, et al., "A versatile SOI BiCMOS technology with complementary lateral BJT's," IEEE IEDM 92, 453-456 (1992), also provided similar schemes.
For technologies utilizing the shallow trench isolation and planarization approach, the integration of SOI with SiGe BiCMOS suffers from the problem of processing compatibility. For partially depleted SOI silicon CMOS, the thin silicon film on top of the buried oxide should be about 0.1 .mu.m to 0.2 .mu.m thick, whereas the thickness of the silicon collector in the SiGe HBT (underneath the SiGe base layer) should be about 0.5 .mu.m, substantially thicker than the CMOS silicon.
It is therefore the objective of the present disclosure to provide an integration scheme to fabricate SiGe HBT on a partially depleted silicon SOI CMOS circuits.